1. Field of the Invention
The present invention provides a semiconductor structure and a method of forming the same, and more particularly, the present invention provides a semiconductor structure with novel aligning marks and method of making the same.
2. Description of the Prior Art
Micro-processor systems comprised of integrated circuits (IC) are ubiquitous devices in modern society, being utilized in such diverse fields as automatic control electronics, mobile communication devices and personal computers. With the development of technology and the increasingly imaginative applications of electrical products, IC devices are becoming smaller, more delicate and more diversified.
With increasing miniaturization of semiconductor devices, it is crucial to maintain the efficiency of miniaturized semiconductor devices in the industry. However, as the size of the field effect transistors (FETs) is continuously shrunk, the development of the planar FETs faces more limitations in the fabricating process thereof. On the other hand, non-planar FETs, such as the fin field effect transistor (FinFET) have three-dimensional structure, not only capable of increasing the contact to the gate but also improving the controlling of the channel region, such that the non-planar FETs have replaced the planar FETs and become the mainstream of the development.
In current techniques, in order to meet the sub-lithographic requirements, a regular photolithography and an etching process are provided to form fin structures in the Fin-FETs. Additionally, the fabrication of semiconductor device also utilizes a pattern transfer technique, such as the sidewall image transfer (SIT) process, to form required fin structures. However, although being beneficial to fabricate the fin structures in finer critical dimension (CD), the pattern transfer technique also complicates the fabrication process of FinFET. Furthermore, the current fabrication process also faces more limitations, such as the misaligning problem since the CD has reached a very small value. Thus, there is still a requirement to have a novel aligning mark specifically used for SIT process for forming the FinFET.